1. Field of the Invention
The present invention relates to a semiconductor device such as an IC, LSI, and VLSI, comprising a high-speed transistor and a high-current (or output) transistor formed in a common substrate.
The subject type of semiconductor device generally comprises high-speed bipolar transistors (or field-effect transistors: FETs) for an arithmetic unit, a logic circuit, memory elements, and the like, and high-current bipolar transistors (or FET's) for an output circuit. Namely, the high-speed transistors operate at a small current and have a low breakdown voltage, but the high-current transistors operate at a large current and at a slower speed than that of the high-speed transistor, and have a high breakdown voltage.
2. Description of the Related Art
In the semiconductor device comprising the high-speed bipolar transistor and the high-current bipolar transistor, a suitable balance of the static common-emitter current gains h.sub.FE of the respective transistors should be maintained, to ensure a stable operation and enable a simple circuit design for the device. A suitable h.sub.FE balance is that where the h.sub.FE of the high-current bipolar transistor is within .+-.30% of that of the high-speed bipolar transistor.
In the prior art, both bipolar transistors have the same emitter width of several micrometers (i.e., more than 1 .mu.m) in view of the h.sub.FE balance.
Recently, to increase the switching (operating) speed of the high-speed bipolar transistor, shallow junction type bipolar transistors have been proposed (e.g., K. Kikuchi et al: "A High-Speed Bipolar LSI Process Using Self-Aligned Double Diffusion Polysilicon Technology", IEEE IEDM, 1986, pp. 420-423; M. Nakamae; "Recent Progress and Future Prospe for VLSI Si Bipolar Transistors", IEEE BCIM, 1987, pp. 5-6). The shallow junction structure is formed by a thermal diffusion of impurities into a silicon substrate (particularly, a silicon epitaxial layer corresponding to a collector region) from a polycrystalline silicon layer doped with the impurities by an ion-implantation process. Preferably, the emitter width is made narrower (less than 1 .mu.m) for a higher operation speed, shallower shallow junction, lower power consumption, and in view of device miniaturization. The high-speed bipolar transistor can operate at 0.1 mA. Since the high-current bipolar transistor can operate at a large current (e.g., 24 to 30 mA), the emitter width should be wider than that of the high-speed bipolar transistor, but a simultaneous fabrication of the bipolar transistor with a narrow emitter width (FIG. 1B) and the bipolar transistor with a wide emitter width (FIG. 1A) leads to an h.sub.FE unbalance. As shown in FIGS. 1A and 1B, base regions 51a and 51b having the same depth are simultaneously formed in collector regions 52a and 52b, which are portions of an epitaxial Si layer on an Si substrate (not shown). A wide emitter window 53a having an emitter width X of, e.g., 1.5 .mu.m, and a narrow emitter window 54b having an emitter width Y of, e.g., 0.5 .mu.m, are opened in an insulating (SiO.sub.2) layer 54 covering the epitaxial layer, and when a polycrystalline silicon layer 55 having a thickness of, e.g., 100 nm, is deposited over the whole surface by a chemical vapor deposition (CVD) process, a portion 55b of the layer 55 filling the window 53b is thicker than a portion 55a filling the window 53a. The polycrystalline silicon layer 55 is then doped with impurities by an ion-implantation process at the projected range R.sub.p of, e.g., 50 nm. To diffuse the doped impurities into the base regions 51a and 51b, the device is subjected to a heat-treatment at 950.degree. C. for 30 minutes, so that emitter regions 56a and 56b are formed in the base region 51a and 52b, respectively. The emitter region 56a has a depth of, e.g., 150 nm, and the emitter region 56b has a depth of, e.g., 100 nm. The emitter region 56b is shallower (thinner) than the emitter region 56a, because the filling portion 55b includes an undoped portion thicker than that included in the filling portion 55a, and as a result, the active base region thickness Za of the wide emitter 53a is smaller than the Zb of the narrow emitter 53b. In general, the h.sub.FE is in inverse proportion to the amount of impurities in the active base region, and therefore, as the thickness of the active base becomes thinner (i.e., the thickness reduces), the h.sub.FE becomes larger and is not suitably balanced.
To control the h.sub.FE of the high-current bipolar transistor, a multi-emitter structure which accordingly increases the number of the emitter regions, or the elongation of an emitter length, may be adopted, but this leads to an enlargement of the transistor size, which does not allow the desired miniaturization of the device and prevents an increase of the degree of integration.